The invention relates to an output timebase corrector as defined in the precharacterizing part of claim 1, and to a display device comprising such an output timebase corrector as defined in the precharacterizing part of claim 8. The invention also relates to an output timebase correction method as defined in the precharacterizing part of claim 7.
U.S. Pat. 5,150,201 discloses a digital television signal-processing circuit with an analog-to-digital converter (further referred to as A/D converter), a color decoder, a skew filter controlled by a phase-locked loop (further referred to as PLL), a signal processor, a dual-port memory controlled by a clock-phase shifter, and a digital to analog converter (further referred to as D/A converter).
The A/D converter supplies a digitized video signal to the color decoder. The color decoder supplies two color difference signals and a luminance signal to the skew filter. The PLL receives a synchronizing signal present in the digitized video signal, and supplies a control signal to the skew filter. The skew filter supplies orthogonal sampled input video signals to the signal processor to facilitate simple video processing, for example filtering. The signal processor supplies orthogonal sampled output video signals to the dual-port memory. The dual-port memory supplies delayed output video signals to the D/A converter to obtain analog video signals to be supplied to a display device. The A/D converter, the color decoder, the skew filter and an input part of the dual-port memory are clocked with the same first clock signal.
The clock-phase shifter receives the first clock signal and a line flyback signal indicating a timing of a line deflection of the display device to supply a second clock signal to an output part of the dual-port memory and the D/A converter. The second clock is derived from the first clock signal by a clock-phase shifter. In such a clock-phase shifter, the first clock signal enters a chain of delay stages whose overall delay is approximately equal to the period of the first clock signal. The taps of all delay stages are connected to associated locking stages which are locked by applying the line flyback signal. The stored phase value can be obtained from the locking stages as a thermometer code specifying the number of delay stages required to delay the first clock signal.
The dual-port memory converts the orthogonal sampled (with the first clock signal) output video signals into delayed output video samples synchronously with the second clock signal. The delay is controlled by the flyback signal.
It is a drawback of the prior-art that two clocks are needed. Although the two clocks have the same frequency, the phases differ dynamically, thereby causing interference. It is also a drawback of the prior-art that the clock-phase shifter is a very delicate analog circuit having a design which depends on the IC process. Moreover, a calibration of the delays is needed as the analog delays vary with temperature, supply voltage and process spread. Due to the two asynchronous clocks, simulations of the prior-art circuit have to be performed with analog simulators, which is a complication.